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Information & Communication Technology (ICT) Formulas

তথ্য ও যোগাযোগ প্রযুক্তি

HSC ICT logic gates, De Morgan's laws, Boolean algebra theorems, half and full adder expressions.

Other Subjects:PhysicsChemistryGeneral MathematicsHigher MathematicsInformation & Communication Technology (ICT)Biology

HSC - Chapter 3: Number Systems & Digital Devices

12 Formulas
HSCChapter 3

De Morgan's First Law

ডি মরগানের প্রথম সূত্র • Number Systems & Digital Devices

A+B‾=A‾⋅B‾\overline{A + B} = \overline{A} \cdot \overline{B}
NOT(A + B) = NOT(A) * NOT(B)
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HSCChapter 3

De Morgan's Second Law

ডি মরগানের দ্বিতীয় সূত্র • Number Systems & Digital Devices

A⋅B‾=A‾+B‾\overline{A \cdot B} = \overline{A} + \overline{B}
NOT(A * B) = NOT(A) + NOT(B)
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HSCChapter 3

Half Adder Sum

হাফ অ্যাডার যোগফল (Sum) • Number Systems & Digital Devices

S=A⊕B=A‾B+AB‾S = A \oplus B = \overline{A}B + A\overline{B}
S = A XOR B = NOT(A)B + ANOT(B)
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HSCChapter 3

Half Adder Carry

হাফ অ্যাডার ক্যারি (Carry) • Number Systems & Digital Devices

C=A⋅BC = A \cdot B
C = A * B
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HSCChapter 3

Full Adder Sum

ফুল অ্যাডার যোগফল (Sum) • Number Systems & Digital Devices

S=A⊕B⊕CinS = A \oplus B \oplus C_{in}
S = A XOR B XOR C_in

💡 Condition: Sum output bit when adding three binary inputs (A, B, Cin) in a Full Adder circuit.

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HSCChapter 3

Full Adder Carry-out

ফুল অ্যাডার ক্যারি (Carry-out) • Number Systems & Digital Devices

Cout=AB+BCin+CinA=AB+Cin(A⊕B)C_{out} = AB + BC_{in} + C_{in}A = AB + C_{in}(A \oplus B)
C_out = AB + BC_in + C_inA = AB + C_in(A XOR B)

💡 Condition: Carry output generated to higher bit positions in Full Adder addition.

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HSCChapter 3

Positional Number System Expansion

স্থানিক সংখ্যা পদ্ধতির সাধারণ বিস্তার • Number Systems & Digital Devices

N=∑i=−mn−1di⋅ri=dn−1rn−1+⋯+d0r0+d−1r−1+⋯+d−mr−mN = \sum_{i=-m}^{n-1} d_i \cdot r^i = d_{n-1}r^{n-1} + \dots + d_0 r^0 + d_{-1}r^{-1} + \dots + d_{-m}r^{-m}
N = Σ_i=-m^n-1 d_i * r^i = d_n-1r^n-1 + dots + d_0 r^0 + d_-1r^-1 + dots + d_-mr^-m

💡 Condition: General base-r polynomial expansion formula to compute the decimal equivalent value.

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HSCChapter 3

n-bit Two's Complement Range

২-এর পরিপূরকে n-বিট সংখ্যার সীমা • Number Systems & Digital Devices

Range=−2n−1 to +(2n−1−1)\text{Range} = -2^{n-1} \text{ to } +(2^{n-1} - 1)
Range = -2^n-1 to +(2^n-1 - 1)

💡 Condition: Represents the range of signed integers representable in n bits (e.g., -128 to +127 for 8-bit registers).

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HSCChapter 3

Boolean Absorption Laws

বুলিয়ান শোষণ উপপাদ্য • Number Systems & Digital Devices

A+AB=A,A(A+B)=A,A+A‾B=A+BA + AB = A, \quad A(A + B) = A, \quad A + \overline{A}B = A + B
A + AB = A, A(A + B) = A, A + NOT(A)B = A + B

💡 Condition: Reduces logic expression complexity by eliminating redundant literals.

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HSCChapter 3

Consensus Theorem

কনসেনসাস উপপাদ্য • Number Systems & Digital Devices

AB+A‾C+BC=AB+A‾CAB + \overline{A}C + BC = AB + \overline{A}C
AB + NOT(A)C + BC = AB + NOT(A)C

💡 Condition: Eliminates redundant terms in SOP logic expressions where the BC term is redundant.

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HSCChapter 3

Encoder and Decoder Line Relations

এনকোডার ও ডিকোডার লাইন সম্পর্ক • Number Systems & Digital Devices

Encoder: 2n→n,Decoder: n→2n\text{Encoder: } 2^n \to n, \quad \text{Decoder: } n \to 2^n
Encoder: 2^n to n, Decoder: n to 2^n

💡 Condition: Input-to-output channel ratios for standard binary Encoders and Decoders.

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HSCChapter 3

Multiplexer Select Line Formula

মাল্টিপ্লেক্সার নির্বাচন লাইন সূত্র • Number Systems & Digital Devices

2n Data Inputs  ⟹  n Select Lines→1 Output2^n \text{ Data Inputs} \implies n \text{ Select Lines} \to 1 \text{ Output}
2^n Data Inputs implies n Select Lines to 1 Output

💡 Condition: Determines the number of select lines needed to route 2^n input data channels to 1 output.

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❓ Information & Communication Technology (ICT) Board Examination FAQs

Common questions on formula application and exam problem-solving rules

Q1: What are De Morgan's first and second logic theorems?

De Morgan's First Law: A+B‾=Aˉ⋅Bˉ\overline{A + B} = \bar{A} \cdot \bar{B}. Second Law: A⋅B‾=Aˉ+Bˉ\overline{A \cdot B} = \bar{A} + \bar{B}. They allow switching between OR and AND gate logic using inverters.

Q2: What are the Boolean equations for Half Adder and Full Adder circuits?

For Half Adder: S=A⊕B=AˉB+ABˉS = A \oplus B = \bar{A}B + A\bar{B}, C=A⋅BC = A \cdot B. For Full Adder: S=A⊕B⊕CinS = A \oplus B \oplus C_{in}, Cout=AB+BCin+CinAC_{out} = AB + BC_{in} + C_{in}A.

Q3: How is two's complement computed and utilized?

Two's complement is calculated by inverting all binary bits (1's complement) and adding 1 to the LSB: 2′s=1′s+12's = 1's + 1. It allows digital ALUs to perform subtraction using addition circuits.

Q4: What are the fundamental logic gates?

The three primary logic gates are AND (Y=A⋅BY = A \cdot B), OR (Y=A+BY = A + B), and NOT (Y=AˉY = \bar{A}). Universal gates (NAND, NOR) are derived from these base gates.
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